1. Field of the Invention
The present invention relates to computer systems and, more specifically, to systems and methods for providing hardware support for efficient binary translation in computer systems and microprocessors.
2. History of the Prior Art
As more and more new computer system installations become available around the world annually, the problem of providing binary compatibility with the existing software generations in future microprocessor designs becomes even more aggravated. It does not matter how advanced the design of a new microprocessor will be, if the release of the new computer system is not backed by the availability of the software packages expected by customers, such a computer system will end up with a little or no attention at all from the public.
A self-evident solution to this problem is to design a new microprocessor that is able to execute a code built for models available in the market at the hardware level. This solution would not only decrease the efficiency of the new microprocessor and require additional hardware, but it could ruin potential benefits achievable by the new microprocessor design.
Another solution to this problem is based on a complex, resource-and time-consuming process of negotiating with software developers and publishers to support the architecture being developed and provide new, compatible versions of their products. Such a solution would likely result in a lengthy schedule due to possible complex product adaptations, and it would also be error-prone since the already well-tested versions of the software applications would get replaced by the new adaptations without the equivalent degree of coverage testing. Moreover, some of the available products would be left unported, making members of the public unhappy that their new computer system is unable to perform tasks completed easily by their old system.
Yet another solution to the problem of binary compatibility is to provide a binary translation technique that allows one to design a highly advanced microprocessor while preserving the ability for high-performance execution of the code compiled for other earlier-developed wide-spread microprocessor architectures.
Binary translation is a process of converting an instruction stream having instructions for the source microprocessor architecture into an instruction stream composed of instructions for the target microprocessor architecture. The source and the target microprocessor architectures could differ substantially. Using a dynamic binary translation process, which is designed to discover new source code sequences and translate them to semantically equivalent target code sequences at run-time, it becomes possible to design a microprocessor of some new architecture that is still able to execute a complete variety of available software products designed for a different (hence foreign) architecture microprocessor. Not only could foreign applications be translated, but foreign operating systems (OSs) as well could be passed through the binary translation process resulting in complete emulation of the foreign computer system functionality by the new computer system design. The resulting computer system could be bundled with the binary translation system written in the native codes as a part of its firmware. It could be advertised as being able to execute both native applications (if they are planned to be developed for this particular computer system) and a complete set of readily available foreign applications and OSs, providing users with an immediate useful experience.
One of the problems arising during the design of such a binary-translation-based computer system lies in memory management. Emulation of the foreign computer system to the fullest extent possible requires maintaining a foreign-code-perceivable virtual memory (VM) space that is identical to the virtual memory space resulting from execution of the same code on real foreign hardware. Such memory management can be problematic. First, because the memory management unit (MMU) for the new microprocessor design can differ considerably in terms of its organization and functionality (i.e., due to many enhancements implemented to improve native code execution performance) from the MMU of a foreign microprocessor, this might require either giving up all the advancements planned for the native MMU or placing an additional burden of the software (or software-assisted) foreign virtual memory management on the binary translated system, which could reduce the binary translated code execution performance considerably. Moreover, since the existence of the binary-translated-code and the binary translation system itself should not be perceived by the foreign codes being executed, some methods of filtering memory access operations initiated by binary-translated-code need to be provided, resulting in a run-time software-controlled memory access process or other inflexible and cumbersome solutions like a physical memory split. Additionally, the binary translated codes could not only initiate memory access transactions on behalf of the original translated foreign codes, but will also need some means of communication with the run-time support section of the binary translation system, thereby requiring some mechanism to override the filter rules applied or some sort of a gateway to be implemented, possibly reducing the integral performance even more.
If a possibility for running native applications is considered as well, additional difficulties may arise, since simplifying the native MMU design to mimic the foreign MMU design could result in a noticeable performance loss. Also, the possibility of simultaneous execution of the native and foreign applications may significantly escalate existing concerns about memory protection (including protection of the foreign code and data from a possibly buggy native application) and dual OS (native and foreign) cooperation techniques.
Not only do such problems interfere with efficient implementation of current binary translation-based computer system designs, which are usually developed to provide binary compatibility with a single foreign architecture, but they also inhibit the development of more advanced solutions providing binary compatibility with multiple foreign architectures. Each new supported foreign architecture requires another dimension added to the virtual memory emulation layer of the binary translation system, resulting in implementation of another translation scheme, other memory access filtering rules and other memory content protection measures, all increasing the complexity and reducing performance of the resulting computer system.
It is therefore desirable to provide systems and methods that overcome these obstacles and provide developers with more power to create a computer system that can execute applications from a multitude of distinct foreign computer architectures, allowing such a computer system to achieve compatibility levels unattainable before. Such a single system could not only be viewed as a natural upgrade path by all users utilizing the different supported foreign computer systems, but it would also provide a unique experience of its own, for example giving users the opportunity to run best-of-breed applications available for different foreign architectures simultaneously on a single computer system.